https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120660
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Philipp Tomsich <ptoms...@gcc.gnu.org>: https://gcc.gnu.org/g:fa1919d3216d2a57cb086ca2e6fcdb8548de04c2 commit r16-2609-gfa1919d3216d2a57cb086ca2e6fcdb8548de04c2 Author: Konstantinos Eleftheriou <konstantinos.elefther...@vrull.eu> Date: Fri Jul 18 04:46:41 2025 -0700 asf: Fix case of multiple stores with base offset [PR120660] When having multiple stores with the same offset as the load, in the case that we are eliminating the load, we were generating a mov instruction for both of them, leading to the overwrite of the register containing the loaded value. This patch fixes this issue by generating a mov instruction only for the first store in the store-load sequence that has the same offset as the load. For the next ones that might be encountered, we use bit-field insertion. Bootstrapped/regtested on AArch64 and x86_64. PR rtl-optimization/120660 gcc/ChangeLog: * avoid-store-forwarding.cc (process_store_forwarding): Fix instruction generation when haveing multiple stores with base offset. gcc/testsuite/ChangeLog: * gcc.dg/pr120660.c: New test.
