https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118241
--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Vineet Gupta <vine...@gcc.gnu.org>: https://gcc.gnu.org/g:f2a3ab7ebf3c40da77f54e8329272fe048ec48a6 commit r16-2032-gf2a3ab7ebf3c40da77f54e8329272fe048ec48a6 Author: Vineet Gupta <vine...@rivosinc.com> Date: Fri Jul 4 12:33:51 2025 -0700 RISC-V: prefetch: fix LRA failing to allocate reg [PR118241] prefetch was recently fixed/tightened (with Q reg constraint) to only support right address patterns (REG or REG+D with lower 5 bits clear). However in some cases that's too restrictive for LRA and it fails to allocate a reg resulting in following ICE... | gcc/testsuite/gcc.target/riscv/pr118241-b.cc:31:19: error: unable to generate reloads for: | 31 | void m() { a.l(); } | | ^ |(insn 26 25 27 7 (prefetch (mem/f:DI (plus:DI (reg/f:DI 143 [ _5 ]) | (const_int 56 [0x38])) [5 _5->batch[6]+0 S8 A64]) | (const_int 0 [0]) | (const_int 3 [0x3])) "gcc/testsuite/gcc.target/riscv/pr118241-b.cc":18:29 498 {prefetch} | (expr_list:REG_DEAD (reg/f:DI 142 [ _5->batch[6] ]) | (nil))) |during RTL pass: reload Fix that by providing a fallback alternative register constraint to reload the address. PR target/118241 gcc/ChangeLog: * config/riscv/riscv.md (prefetch): Add alternative "r". gcc/testsuite/ChangeLog: * gcc.target/riscv/pr118241-b.cc: New test. Signed-off-by: Vineet Gupta <vine...@rivosinc.com>
