[Bug target/120920] New: RISC-V: Possible optimization of bswap when zbb is enabled

[Dusan.Stojkovic--- via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120920

            Bug ID: 120920
           Summary: RISC-V: Possible optimization of bswap when zbb is
                    enabled
           Product: gcc
           Version: 16.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: dusan.stojko...@rt-rk.com
  Target Milestone: ---

The following function is taken from the x86 testsuite (xchg-4.c):

```
unsigned int bswap8 (unsigned int val)
{
  return (val & 0xffff0000) | ((val & 0xff00) >> 8) | ((val & 0xff) << 8);
}
```

GCC generates the following assembly:
```
bswap8:
        rev8    a5,a0
        li      a4,-65536
        srai    a5,a5,32
        and     a5,a5,a4
        roriw   a5,a5,16
        and     a0,a0,a4
        or      a0,a0,a5
        sext.w  a0,a0
        ret
```

A possibility for improvement for rv64 could be:
```
bswap8:
        rev8 t0, a0
        srli t1, a0, 16
        srai t0, t0, 48
        slli t1, t1, 16
        or   a0, t1, t0
        ret
```

This case swaps bytes 0:7 and 7:15. The shift amount could be set to change
depending on which set of 8 bytes are to be swapped.