[Bug target/120659] ICE: in riscv_sched_variable_issue, at config/riscv/riscv.cc:9879 with -O2 -mcpu=sifive-x280

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120659

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <k...@gcc.gnu.org>:

https://gcc.gnu.org/g:c8cb537fdbdbc9e1c77ec389bcb99ad87b15cb92

commit r16-1779-gc8cb537fdbdbc9e1c77ec389bcb99ad87b15cb92
Author: Kito Cheng <kito.ch...@sifive.com>
Date:   Tue Jun 17 16:20:19 2025 +0800

    RISC-V: Adding B ext, fp16 and missing scalar instruction type for sifive-7
pipeline model [PR120659]

    gcc/ChangeLog:

            PR target/120659
            * config/riscv/sifive-7.md: Add B extension, fp16 and missing
            scalar instruction type for sifive-7 pipeline model.

    gcc/testsuite/ChangeLog:

            PR target/120659
            * gcc.target/riscv/pr120659.c: New test.