[Bug target/119100] RISC-V: missed opportunities for vector-scalar instructions

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119100

--- Comment #8 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:92e1893e0155b6b3baef2a935efd5936d23a67ea

commit r16-1659-g92e1893e0155b6b3baef2a935efd5936d23a67ea
Author: Paul-Antoine Arras <par...@baylibre.com>
Date:   Tue Jun 24 15:42:50 2025 -0600

    RISC-V: Add patterns for vector-scalar multiply-(subtract-)accumulate
[PR119100]

    This pattern enables the combine pass (or late-combine, depending on the
case)
    to merge a vec_duplicate into a plus-mult or minus-mult RTL instruction.

    Before this patch, we have two instructions, e.g.:
      vfmv.v.f       v6,fa0
      vfmacc.vv      v2,v6,v4

    After, we get only one:
      vfmacc.vf      v2,fa0,v4

            PR target/119100

    gcc/ChangeLog:

            * config/riscv/autovec-opt.md (*<optab>_vf_<mode>): Handle both add
and
            acc FMA variants.
            * config/riscv/vector.md (*pred_mul_<optab><mode>_scalar_undef):
New.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmacc and
vfmsac.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h: Add support for
acc
            variants.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h: Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: Define
            TEST_OUT.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c:
Likewise.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: New
test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c: New
test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c: New
test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: New
test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c: New
test.
            * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c: New
test.