[Bug middle-end/120687] RISC-V: very poor vector code gen for LMbench bw_mem test case

[bergner at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120687

Peter Bergner <bergner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|riscv64-unknown-linux-gnu   |riscv64-unknown-linux-gnu,
                   |                            |aarch64-linux
     Ever confirmed|0                           |1
          Component|target                      |middle-end
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2025-06-18

--- Comment #4 from Peter Bergner <bergner at gcc dot gnu.org> ---
(In reply to ktkachov from comment #2)
> I similarly see this generates ~200 lines of assembly for aarch64 compared
> to ~20 with Clang so I'd mark it as target-independent.
> I think I remember a bug in the past about the need for loop rerolling
> functionality in the vectoriser

Ok, confirmed, adding arch64-linux and moving to a middle-end issue.