https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120587
--- Comment #3 from Stafford Horne <shorne at gcc dot gnu.org> --- One comment left by Dimitar on the mail chain was: > Another patch I intend to merge tomorrow will tighten the checks even > more: https://gcc.gnu.org/pipermail/gcc-patches/2025-June/685837.html > > Seeing that or1k_hard_regno_mode_ok forbids SImode for class FLAG_REGS, > the validate_subreg may once again start rejecting subregs for or1k. After that patch the issue returns again. I have the following fix thought which allows convert_mode_scalar to bypass trying to use subregs and use "sign extension" instead as a method to move the SR[F] details into a register. diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 627e40084b3..66e5af10a98 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -515,6 +515,24 @@ (ne:SI (reg:BI SR_F_REGNUM) (const_int 0)))] "") +(define_expand "zero_extendbisi2" + [(set (match_operand:SI 0 "register_operand" "") + (zero_extend:SI (match_operand:BI 1 "register_operand" "")))] + "" +{ + emit_insn(gen_sne_sr_f (operands[0])); + DONE; +}) + +(define_expand "extendbisi2" + [(set (match_operand:SI 0 "register_operand" "") + (sign_extend:SI (match_operand:BI 1 "register_operand" "")))] + "" +{ + emit_insn(gen_sne_sr_f (operands[0])); + DONE; +}) + This fixes the ICE issue, but it points out that the ce1 pass is not able to perform good optimizations on OpenRISC. This is because openrisc very early (during expand) converts branch statements to "set flag" and "branch if flag". If we would maintain the branch RTL in the original form a bit longer I think the ce1 pass could have a better chance to optimize.
