https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120601
Bug ID: 120601
Summary: Add support for nvptx's adc, add.cc and friends via
uaddc{si,di}5 optabs
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: roger at nextmovesoftware dot com
Target Milestone: ---
Target: nvptx-*-*
nvptx supports instructions for integer addition and subtraction optionally
setting a carry flag, and honoring the carry flag from a previous addition or
subtraction. These instructions intended to assist extended precison
arithmetic can be used to implement GCC's __builtin_{add,sub}_overflow family
of functions (as provided by Jakub's solution to PR middle-end/79173).
Usually, supporting this functionality would just require adding the necessary
named patterns to the backend for uaddc<mode>5 and usubc<mode>5, but things are
(currently) a little more complicated for nvptx, as the machine description
doesn't currently model the CC.CF flag, which (I believe) requires adding a new
register, register class, updating numerous hard register indexed arrays etc.
Alas, such a fundamental change to a backend is beyond my comfort zone, so I'll
simply file an enhancement request in bugzilla, requesting that a backend
maintainer or more adventurous contributor attempt the necessary changes.
SImode add.cc, addc, addc.cc, sub.cc, subc, and subc.cc are available on all
nvptx target architectures and were introduced in PTX ISA 1.2. DImode versions
of these instructions requires sm_20 or higher, and were introduced in PTX ISA
4.3.
https://docs.nvidia.com/cuda/parallel-thread-execution/#extended-precision-integer-arithmetic-instructions
Thanks in advance.
