https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120479
--- Comment #2 from Paolo Bonzini <bonzini at gnu dot org> --- a7 is from line (1) which is a sltu instruction, so it has itself only bit 0 set. I think it should be possible to generate (if_then_else (eq/ne X (const_int 0)) Y (const_int 0)) from (and (eq/ne X (const_int 0)) Y), either in combine or in the RISC-V machine description, if Y has nonzero bits of 1.
