https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114512
--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:4cd741dcbd3729863ab005d7ec61a890e0a193f1 commit r16-411-g4cd741dcbd3729863ab005d7ec61a890e0a193f1 Author: Shreya Munnangi <smunnan...@ventanamicro.com> Date: Tue May 6 06:38:00 2025 -0600 [RISC-V][PR middle-end/114512] Recognize more bext idioms for RISC-V This is Shreya's next chunk of work. When I was looking for good bugs for her to chase down I cam across PR114512. While the bug isn't necessarily a RISC-V specific bug, its testcases did show how we were failing to recognize certain bit extraction idioms and how the lispy nature of RTL allows us to tackle these issues in the combiner. First, the bit position may be masked. The RISC-V port does not define SHIFT_COUNT_TRUNCATED for valid reasons. So if we want to optimize away a mask that matches what the hardware will do, we need suitable insns that include that explicit masking. In addition to needing to incorporate masking, the masking may happen in a subword mode. So we need to recognize the mask wrapped in a zero extension. Those two captured the most common cases. We can also have a single bit extraction implemented as a left shift of the bit into the sign bit, then a right shift by the size of a word - 1. These are less common, but we did cover the case derived from the upstream bug report as well as one class seen reviewing the instruction stream for spec2017. Finally, extracting a single bit at a variable position from a constant as seen with some regularity in spec2017. In that scenario, combine's chosen split point wasn't ideal (I forget what it selected, but it definitely wasn't helpful). So we've got a new splitter for this case as well. Earlier versions of this have gone through my tester as well as a bootstrap and regression cycle. This version has just gone through a cycle in my tester (but missed today's bootstrap cycle). Waiting on the upstream pre-commit tester to render its verdict, but the plan is to commit on Shreya's behalf once that's clean. Co-authored-by: Jeff Law <j...@ventanamicro.com> PR middle-end/114512 gcc/ * config/riscv/bitmanip.md (bext* patterns): New patterns for bext recognition plus splitter for extracting variable bit from a constant. * config/riscv/predicates.md (bitpos_mask_operand): New predicate. gcc/testsuite/ * gcc.target/riscv/pr114512.c: New test.
