[Bug target/119971] [15/16 Regression] RISC-V: Wrong code with bitmanip extension

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119971

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|RISC-V: Wrong code with     |[15/16 Regression] RISC-V:
                   |bitmanip extension          |Wrong code with bitmanip
                   |                            |extension
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2025-04-27
     Ever confirmed|0                           |1
   Target Milestone|---                         |15.2

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed. This is due to this split:
```
(define_insn_and_split "*<optab>si3_extend_mask"
  [(set (match_operand:DI                   0 "register_operand" "= r")
        (sign_extend:DI
            (any_shift:SI
             (match_operand:SI 1 "register_operand" "  r")
             (match_operator 4 "subreg_lowpart_operator"
              [(and:GPR
                (match_operand:GPR 2 "register_operand" " r")
                (match_operand 3 "const_si_mask_operand"))]))))]
  "TARGET_64BIT"
  "#"
  "&& 1"
  [(set (match_dup 0)
        (sign_extend:DI
         (any_shift:SI (match_dup 1)
                       (match_dup 2))))]
  "operands[2] = gen_lowpart (QImode, operands[2]);"
  [(set_attr "type" "shift")
   (set_attr "mode" "SI")])

```

And then interacting with the bext instruction pattern.

r14-947-g6da6ed95c9ca24