https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118410
--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:874f4c164749f1ed5b60ddf1d4533c8f4ba627a1 commit r16-40-g874f4c164749f1ed5b60ddf1d4533c8f4ba627a1 Author: Jeff Law <j...@ventanamicro.com> Date: Sat Apr 19 12:30:42 2025 -0600 [RISC-V][PR target/118410] Improve code generation for some logical ops I'm posting this on behalf of Shreya Munnangi who is working as an intern with me. I've got her digging into prerequisites for removing mvconst_internal and would prefer she focus on that rather than our patch process at this time. -- We can use the orn, xnor, andn instructions on RISC-V to improve the code generated logical operations when one operand is a constant C where synthesizing ~C is cheaper than synthesizing C. This is going to be an N -> N - 1 splitter rather than a define_insn_and_split. A define_insn_and_split can obviously work, but has multiple undesirable effects in general. As a result of implementing as a simple define_split we're not supporting AND at this time. We need to clean up the mvconst_internal situation first after which supporting AND is trivial. This has been tested in Ventana's CI system as well as my tester. Obviously we'll wait for the pre-commit tester to run before moving forward. PR target/118410 gcc/ * config/riscv/bitmanip.md (logical with constant argument): New splitter for cases where synthesizing ~C is cheaper than synthesizing the original constant C. gcc/testsuite/ * gcc.target/riscv/pr118410-1.c: New test. * gcc.target/riscv/pr118410-2.c: Likewise. Co-authored-by: Jeff Law <j...@ventanamicro.com>
