[Bug target/116593] internal compiler error: in get_attr_type, at config/riscv/riscv.md:28048 with -O2 -O3 when compiling for risc-v xtheadvector

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116593

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Ma Jin <ma...@gcc.gnu.org>:

https://gcc.gnu.org/g:2631ac38d9b2a9def13a04c1e1fefb3871e420ab

commit r14-11583-g2631ac38d9b2a9def13a04c1e1fefb3871e420ab
Author: Jin Ma <ji...@linux.alibaba.com>
Date:   Tue Jan 21 10:46:37 2025 -0700

    RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not
get a non-zero immediate

    Although we have handled the vl of XTheadVector correctly in the
    expand phase and predicates, the results show that the work is
    still insufficient.

    In the curr_insn_transform function, the insn is transformed from:
    (insn 69 67 225 12 (set (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0  S[128, 128]
A32])
            (if_then_else:RVVM8SF (unspec:RVVMF4BI [
                        (const_vector:RVVMF4BI repeat [
                                (const_int 1 [0x1])
                            ])
                        (reg:DI 209)
                        (const_int 0 [0])
                        (reg:SI 66 vl)
                        (reg:SI 67 vtype)
                    ] UNSPEC_VPREDICATE)
                (reg/v:RVVM8SF 143 [ _xx ])
                (mem:RVVM8SF (reg/f:DI 218 [ _77 ]) [0  S[128, 128] A32])))
         (expr_list:REG_DEAD (reg/v:RVVM8SF 143 [ _xx ])
            (nil)))
    to
    (insn 69 284 225 11 (set (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ]
[218]) [0  S[128, 128] A32])
            (if_then_else:RVVM8SF (unspec:RVVMF4BI [
                        (const_vector:RVVMF4BI repeat [
                                (const_int 1 [0x1])
                            ])
                        (const_int 1 [0x1])
                        (const_int 0 [0])
                        (reg:SI 66 vl)
                        (reg:SI 67 vtype)
                    ] UNSPEC_VPREDICATE)
                (reg/v:RVVM8SF 104 v8 [orig:143 _xx ] [143])
                (mem:RVVM8SF (reg/f:DI 18 s2 [orig:218 _77 ] [218]) [0  S[128,
128] A32])))
         (nil))

    Looking at the log for the reload pass, it is found that "Changing pseudo
209 in
    operand 3 of insn 69 on equiv 0x1".
    It converts the vl operand in insn from the expected register(reg:DI 209)
to the
    constant 1(const_int 1 [0x1]).

    This conversion occurs because, although the predicate for the vl operand
is
    restricted by "vector_length_operand" in the pattern, the constraint is
still
    "rK", which allows the transformation.

    The issue is that changing the "rK" constraint to "rJ" for the constraint
of vl
    operand in the pattern would prevent this conversion, But unfortunately
this will
    conflict with RVV (RISC-V Vector Extension).

    Based on the review's recommendations, the best solution for now is to
create
    a new constraint to distinguish between RVV and XTheadVector, which is
exactly
    what this patch does.

            PR target/116593

    gcc/ChangeLog:

            * config/riscv/constraints.md (vl): New.
            * config/riscv/thead-vector.md: Replacing rK with rvl.
            * config/riscv/vector.md: Likewise.

    gcc/testsuite/ChangeLog:

            * g++.target/riscv/rvv/rvv.exp: Enable testsuite of XTheadVector.
            * g++.target/riscv/rvv/xtheadvector/pr116593.C: New test.

    (cherry picked from commit 3024b12f2cde5db3bf52b49b07e32ef3065929fb)