https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119681
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target|Aarch64 x86_64 |Aarch64 x86_64 riscv
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Artemiy Volkov from comment #3)
> The (draft) patch that I have was originally conceived to be useful for a
> very small RISC-V core with load latency = 1, where the removal of these
> moves is beneficial, but I'm observing a 0.5% improvement for Coremark
> (compiled with -O2 -funroll-all-loops) even on a Cortex-A53.
Oh I see this is not a big core. Even the successor of a53 cores have this kind
of rename for free.
Do you have benchmarks besides coremarks? Like say for spec 2017 or the
original eembc benchmarks? How much is the compile time increase?
Does this pattern show up in other locations besides coremarks?
