https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119554

Li Pan <pan2.li at intel dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jeffreyalaw at gmail dot com,
                   |                            |juzhe.zhong at rivai dot ai,
                   |                            |kito.cheng at gmail dot com,
                   |                            |pan2.li at intel dot com,
                   |                            |rdapp at gcc dot gnu.org

--- Comment #1 from Li Pan <pan2.li at intel dot com> ---
It should be fixed in gcc-15 I guess, CC RISC-V relatives.

test:

vsetivli        zero,4,e32,m1,tu,ma // tu here.
vle32.v v1,0(a0)
lui     a5,%hi(.LC1)
addi    a5,a5,%lo(.LC1)                                                        
                                                                               
                                                                               
                             vlm.v   v0,0(a5)                                  
                                                                               
                                                                               
                                                          vmv.v.i v4,0         
                                                                               
                                                                               
                                                                               
       vsrl.vi v2,v1,31                                                        
                                                                               
                                                                               
                                    vsll.vi v1,v1,1                            
                                                                               
                                                                               
                                                                 vslideup.vi   
 v3,v2,1                                                                       
                                                                               
                                                                               
              vslidedown.vi   v2,v2,3                                          
                                                                               
                                                                               
                                           vcompress.vm    v3,v4,v0            
                                                                               
                                                                               
                                                                        vmv.x.s
a5,v2                                                                          
                                                                               
                                                                               
                     vor.vv  v1,v1,v3                                          
                                                                               
                                                                               
                                                  vse32.v v1,0(a0)             
                                                                               
                                                                               
                                                                              
beq     a5,zero,.L6                                                            
                                                                               
                                                                               
                             vmv.x.s a5,v1                                     
                                                                               
                                                                               
                                                          xori    a5,a5,135    
                                                                               
                                                                               
                                                                               
       sw      a5,0(a0)

QEMU_CPU=rv64,zvfh=true,vlen=128,rvv_ta_all_1s=true,rvv_ma_all_1s=true,v=true,vext_spec=v1.0
~/bin/qemu/bin/qemu-riscv64 test.elf
test  result  d04dabf1 8e88021b 99a51933 c6f03ac9

riscv64-unknown-elf-gcc (g4cdc5b505fe) 15.0.1 20250331 (experimental)
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