[Bug target/119473] [15 Regression] __builtin_ia32_vaesdec_v32qi() emits wrong base register with -mvaes -O2 -mapxf -m64

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119473

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Hu <hu...@gcc.gnu.org>:

https://gcc.gnu.org/g:e5cfa7f797b79613e5483786484567b9ca72db06

commit r15-9117-ge5cfa7f797b79613e5483786484567b9ca72db06
Author: Hu, Lin1 <lin1...@intel.com>
Date:   Wed Mar 26 16:15:52 2025 +0800

    i386: Add attr_isa for vaes patterns to sync with attr gpr16. [pr119473]

    For vaes patterns with jm constraint and gpr16 attr, it requires "isa"
    attr to distinct avx/avx512 alternatives in ix86_memory_address_reg_class.
    Also adds missing type and mode attributes for those vaes patterns.

    gcc/ChangeLog:

            PR target/119473
            * config/i386/sse.md
            (vaesdec_<mode>): Set attr "isa" as "avx,vaes_avx512vl", "type" as
            "sselog1", "mode" as "TI".
            (vaesdeclast_<mode>): Ditto.
            (vaesenc_<mode>): Ditto.
            (vaesenclast_<mode>): Ditto.

    gcc/testsuite/ChangeLog:

            PR target/119473
            * gcc.target/i386/pr119473.c: New test.

    Co-authored-by: Hongyu Wang <hongyu.w...@intel.com>