[Bug target/119464] VEC_PERM_EXPR not optimized to pslldq instruction for AVX2 and AVX512BW

[mkretz at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119464

--- Comment #3 from Matthias Kretz (Vir) <mkretz at gcc dot gnu.org> ---
Good point on recognizing even more of these shifts. Here's an extended test
case: https://compiler-explorer.com/z/6MKPzxn9T

typedef unsigned long long V2 __attribute__ ((vector_size (16)));
typedef unsigned long long V4 __attribute__ ((vector_size (32)));
typedef unsigned long long V8 __attribute__ ((vector_size (64)));

typedef unsigned char C16 __attribute__ ((vector_size (16)));
typedef unsigned char C32 __attribute__ ((vector_size (32)));
typedef unsigned char C64 __attribute__ ((vector_size (64)));

C16
shiftleft1 (C16 x)
{
  return __builtin_shufflevector (x, C16 (), 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
                                  10, 11, 12, 13, 14);
}

C16
shiftright1 (C16 x)
{
  return __builtin_shufflevector (x, C16 (), 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
                                  12, 13, 14, 15, 16);
}

C16
shiftleft3 (C16 x)
{
  return __builtin_shufflevector (x, C16 (), 16, 16, 16, 0, 1, 2, 3, 4, 5, 6,
                                  7, 8, 9, 10, 11, 12);
}

V2
shiftleft8 (V2 x)
{
  return __builtin_shufflevector (x, V2 (), 2, 0);
}

C32
shiftleft1 (C32 x)
{
  return __builtin_shufflevector (x, C32 (), 32, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
                                  10, 11, 12, 13, 14, 32, 16, 17, 18, 19, 20,
                                  21, 22, 23, 24, 25, 26, 27, 28, 29, 30);
}

C32
shiftright1 (C32 x)
{
  return __builtin_shufflevector (x, C32 (), 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
                                  12, 13, 14, 15, 32, 17, 18, 19, 20, 21, 22,
                                  23, 24, 25, 26, 27, 28, 29, 30, 31, 32);
}

C32
shiftleft5 (C32 x)
{
  return __builtin_shufflevector (x, C32 (), 32, 32, 32, 32, 32, 0, 1, 2, 3, 4,
                                  5, 6, 7, 8, 9, 10, 32, 32, 32, 32, 32, 16,
                                  17, 18, 19, 20, 21, 22, 23, 24, 25, 26);
}

C32
shiftright5 (C32 x)
{
  return __builtin_shufflevector (x, C32 (), 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
                                  15, 32, 32, 32, 32, 32, 21, 22, 23, 24, 25,
                                  26, 27, 28, 29, 30, 31, 32, 32, 32, 32, 32);
}

V4
shiftleft8 (V4 x)
{
  return __builtin_shufflevector (x, V4 (), 4, 0, 4, 2);
}

C64
shiftleft1 (C64 x)
{
  return __builtin_shufflevector (
      x, C64 (), 64, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 64, 16,
      17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 64, 32, 33, 34,
      35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 64, 48, 49, 50, 51, 52,
      53, 54, 55, 56, 57, 58, 59, 60, 61, 62);
}

C64
shiftright1 (C64 x)
{
  return __builtin_shufflevector (
      x, C64 (), 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 64, 17, 18,
      19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 64, 33, 34, 35, 36,
      37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 64, 49, 50, 51, 52, 53, 54,
      55, 56, 57, 58, 59, 60, 61, 62, 63, 64);
}

V8
shiftleft8 (V8 x)
{
  return __builtin_shufflevector (x, V8 (), 8, 0, 8, 2, 8, 4, 8, 6);
}