https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119267
Bug ID: 119267 Summary: RISC-V: gcc generates vsetvli with wrong LMUL with extended assembly Product: gcc Version: 14.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: mperotti at iis dot ee.ethz.ch Target Milestone: --- Created attachment 60739 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=60739&action=edit Content of "a-bug.i" I experienced an issue when writing RISC-V V assembly code in a .c file. Function content: ``` asm volatile ("vsetvli t0, %0, e8, m1, ta, ma" :: "r" (16) : "t0", "vtype", "vl"); volatile unsigned char Va[] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; asm volatile ("vle8.v v1, (%0)":: "r"(Va)); volatile unsigned char Vb[] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; asm volatile ("vle8.v v2, (%0)":: "r"(Vb)); asm volatile ("vsetvli t0, %0, e16, m1, ta, ma" :: "r" (16) : "t0", "vtype", "vl"); volatile unsigned short int Vc[] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; asm volatile ("vle16.v v1, (%0)":: "r"(Vc)); volatile unsigned short int Vd[] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; asm volatile ("vle16.v v2, (%0)":: "r"(Vd)); ``` Fragment of the objdump: ``` vsetvli t0,a5,e16,m1,ta,ma lui a5,0x10 addi a4,a5,488 # 101e8 <_start+0x40> addi a5,s0,-80 vsetivli zero,4,e64,m8,ta,ma vle64.v v8,(a4) vsetivli zero,4,e64,m8,ta,ma vse64.v v8,(a5) addi a5,s0,-80 vle16.v v1,(a5) ``` gcc inserts vsetivli instructions that overwrite the LMUL I previously set without setting it back so that my "vle16.v v1" instruction becomes illegal. The code of a-bug.i is attached. ------------------------------------------------- Command line: ${path1}/riscv64-unknown-elf-gcc -v -save-temps -Wall -Wextra -nostartfiles -march=rv64gv -mabi=lp64 bug.c Warning: No warnings ------------------------------------------------- Target: riscv64-unknown-elf Configured with: ${path0}/configure --target=riscv64-unknown-elf --prefix=${path1}/riscv-gcc --disable-shared --disable-threads --enable-languages=c,c++ --with-pkgversion=g04696df09 --with-system-zlib --enable-tls --with-newlib --with-sysroot=${path1}/riscv-gcc/riscv64-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../gcc --enable-multilib --with-abi=lp64d --with-arch=rv64gcv --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-Os -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medany' gcc version 14.2.0 (g04696df09) ------------------------------------------------- Extended command output: Using built-in specs. COLLECT_GCC=../../install/riscv-gcc/bin/riscv64-unknown-elf-gcc COLLECT_LTO_WRAPPER=${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/lto-wrapper Target: riscv64-unknown-elf Configured with: ${path}/toolchain/riscv-gnu-toolchain/build/../gcc/configure --target=riscv64-unknown-elf --prefix=${path}/install/riscv-gcc --disable-shared --disable-threads --enable-languages=c,c++ --with-pkgversion=g04696df09 --with-system-zlib --enable-tls --with-newlib --with-sysroot=${path}/install/riscv-gcc/riscv64-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=../../gcc --enable-multilib --with-abi=lp64d --with-arch=rv64gcv --with-tune=rocket --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-Os -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-Os -mcmodel=medany' Thread model: single Supported LTO compression algorithms: zlib gcc version 14.2.0 (g04696df09) COLLECT_GCC_OPTIONS='-v' '-save-temps' '-nostartfiles' '-march=rv64gv' '-mabi=lp64' '-Wall' '-Wextra' '-mtune=rocket' '-misa-spec=20191213' '-march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b' '-dumpdir' 'a-' ${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/cc1 -E -quiet -v bug.c -march=rv64gv -mabi=lp64 -mtune=rocket -misa-spec=20191213 -march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b -Wall -Wextra -fpch-preprocess -o a-bug.i ignoring nonexistent directory "${path}/install/riscv-gcc/riscv64-unknown-elf/usr/local/include" ignoring duplicate directory "${path}/install/riscv-gcc/riscv64-unknown-elf/include" #include "..." search starts here: #include <...> search starts here: ${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/include ${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/include-fixed ${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/../../../../riscv64-unknown-elf/include End of search list. COLLECT_GCC_OPTIONS='-v' '-save-temps' '-nostartfiles' '-march=rv64gv' '-mabi=lp64' '-Wall' '-Wextra' '-mtune=rocket' '-misa-spec=20191213' '-march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b' '-dumpdir' 'a-' ${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/cc1 -fpreprocessed a-bug.i -quiet -dumpdir a- -dumpbase bug.c -dumpbase-ext .c -march=rv64gv -mabi=lp64 -mtune=rocket -misa-spec=20191213 -march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b -Wall -Wextra -version -o a-bug.s GNU C17 (g04696df09) version 14.2.0 (riscv64-unknown-elf) compiled by GNU C version 14.2.0, GMP version 6.2.1, MPFR version 4.1.0, MPC version 1.2.1, isl version isl-0.24-GMP GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072 Compiler executable checksum: bba804f6629957e309ef1ba78c198dd2 COLLECT_GCC_OPTIONS='-v' '-save-temps' '-nostartfiles' '-march=rv64gv' '-mabi=lp64' '-Wall' '-Wextra' '-mtune=rocket' '-misa-spec=20191213' '-march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b' '-dumpdir' 'a-' ${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/../../../../riscv64-unknown-elf/bin/as -v --traditional-format -march=rv64gv -march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b -mabi=lp64 -misa-spec=20191213 -o a-bug.o a-bug.s GNU assembler version 2.43.1 (riscv64-unknown-elf) using BFD version (GNU Binutils) 2.43.1 COMPILER_PATH=${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/:${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/:${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/:${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/:${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/:${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/../../../../riscv64-unknown-elf/bin/ LIBRARY_PATH=${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/:${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/../../../../riscv64-unknown-elf/lib/:${path}/install/riscv-gcc/riscv64-unknown-elf/lib/ COLLECT_GCC_OPTIONS='-v' '-save-temps' '-nostartfiles' '-march=rv64gv' '-mabi=lp64' '-Wall' '-Wextra' '-mtune=rocket' '-misa-spec=20191213' '-march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b' '-dumpdir' 'a.' ${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/collect2 -plugin ${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/liblto_plugin.so -plugin-opt=${path}/install/riscv-gcc/libexec/gcc/riscv64-unknown-elf/14.2.0/lto-wrapper -plugin-opt=-fresolution=a.res -plugin-opt=-pass-through=-lgcc -plugin-opt=-pass-through=-lc -plugin-opt=-pass-through=-lgloss -plugin-opt=-pass-through=-lgcc --sysroot=${path}/install/riscv-gcc/riscv64-unknown-elf -melf64lriscv -X -L${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0 -L${path}/install/riscv-gcc/lib/gcc/riscv64-unknown-elf/14.2.0/../../../../riscv64-unknown-elf/lib -L${path}/install/riscv-gcc/riscv64-unknown-elf/lib a-bug.o -lgcc --start-group -lc -lgloss --end-group -lgcc COLLECT_GCC_OPTIONS='-v' '-save-temps' '-nostartfiles' '-march=rv64gv' '-mabi=lp64' '-Wall' '-Wextra' '-mtune=rocket' '-misa-spec=20191213' '-march=rv64imafdv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b' '-dumpdir' 'a.' ------------------------------------------------- Thank you in advance.