[Bug rtl-optimization/119115] [15 regression] RISC-V: miscompile at -O3 with zvl256b -fsigned-char -fwrapv since r15-1579-g792f97b44ff

[rdapp at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119115

--- Comment #5 from Robin Dapp <rdapp at gcc dot gnu.org> ---
The problematic vsetvl is
        vsetvli zero,a3,e16,m1,ta,ma
which was a 
        vsetvli a4,a3,e8,mf2,ta,ma
        vsetvli t1,a3,e8,mf2,ta,ma
with the simple strategy.