[Bug target/119091] New: RISC-V eliminate redundancies in constant synthesis

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119091

            Bug ID: 119091
           Summary: RISC-V eliminate redundancies in constant synthesis
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: law at gcc dot gnu.org
  Target Milestone: ---

Compile on rv64 with -O2:

#define const1 0x0101010101010101ULL 
#define const2 0x0080402010080400ULL 
#define const0 const1
unsigned long long g(unsigned long long occ, const unsigned int sq) {
  return const0 ;
}
unsigned long long f(unsigned long long occ, const unsigned int sq) {
  unsigned long long t= (const0)>>32<<32 ;
  unsigned long long t1= (unsigned int)(const0) ;
  asm("":"+r"(t));
  return t | t1;
}


Results in this for "f":

f:
        li      a0,16842752
        li      a5,16842752
        addi    a5,a5,257
        addi    a0,a0,257
        slli    a0,a0,32
        or      a0,a0,a5
        ret

Obviously there's a redundant li+addi in there.