[Bug target/118931] [15 Regression] RISC-V: rv64gcv miscompile at -O[23] since r15-3228-g771256bcb9d

[pan2.li at intel dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118931

--- Comment #3 from Li Pan <pan2.li at intel dot com> ---
It is a bug of interleaved_stepped when expand_const_vector, the base + i*step
for base1 series may overflow and then the base2 series will OR overflowed bits
to the final result.

I will prepare a fix for this.