https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116351

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:25256ec1df10f2eb183e1c1ab0c890e9fdd94384

commit r15-7625-g25256ec1df10f2eb183e1c1ab0c890e9fdd94384
Author: Pan Li <pan2...@intel.com>
Date:   Wed Feb 19 09:37:51 2025 +0800

    Vect: Fix ICE when vect_verify_loop_lens acts on relevant mode [PR116351]

    This patch would like to fix the ICE similar as below, assump we have
    sample code:

       1   â int a, b, c;
       2   â short d, e, f;
       3   â long g (long h) { return h; }
       4   â
       5   â void i () {
       6   â   for (; b; ++b) {
       7   â     f = 5 >> a ? d : d << a;
       8   â     e &= c | g(f);
       9   â   }
      10   â }

    It will ice when compile with -O3 -march=rv64gc_zve64f
-mrvv-vector-bits=zvl

    during GIMPLE pass: vect
    pr116351-1.c: In function âiâ:
    pr116351-1.c:8:6: internal compiler error: in get_len_load_store_mode,
    at optabs-tree.cc:655
        8 | void i () {
          |      ^
    0x44d6b9d internal_error(char const*, ...)
   
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/diagnostic-global-context.cc:517
    0x44a26a6 fancy_abort(char const*, int, char const*)
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/diagnostic.cc:1722
    0x19e4309 get_len_load_store_mode(machine_mode, bool, internal_fn*,
vec<int, va_heap, vl_ptr>*)
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/optabs-tree.cc:655
    0x1fada40 vect_verify_loop_lens
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/tree-vect-loop.cc:1566
    0x1fb2b07 vect_analyze_loop_2
   
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/tree-vect-loop.cc:3037
    0x1fb4302 vect_analyze_loop_1
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/tree-vect-loop.cc:3478
    0x1fb4e9a vect_analyze_loop(loop*, gimple*, vec_info_shared*)
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/tree-vect-loop.cc:3638
    0x203c2dc try_vectorize_loop_1
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/tree-vectorizer.cc:1095
    0x203c839 try_vectorize_loop
           
/home/pli/gcc/111/riscv-gnu-toolchain/gcc/__RISC-V_BUILD__/../gcc/tree-vectorizer.cc:1212
    0x203cb2c execute

    During vectorization the override_widen pattern matched and then will get
DImode
    as vector_mode in loop_info.  After that the loop_vinfo will step in
vect_analyze_xx
    with below flow:

    vect_analyze_loop_2
     |- vect_pattern_recog // over-widening and set loop_vinfo->vector_mode to
DImode
     |- ...
     |- vect_analyze_loop_operations
       |- stmt_info->def_type == vect_reduction_def
       |- stmt_info->slp_type == pure_slp
       |- vectorizable_lc_phi     // Not Hit
       |- vectorizable_induction  // Not Hit
       |- vectorizable_reduction  // Not Hit
       |- vectorizable_recurr     // Not Hit
       |- vectorizable_live_operation  // Not Hit
       |- vect_analyze_stmt
         |- stmt_info->relevant == vect_unused_in_scope
         |- stmt_info->live == false
         |- p pattern_stmt_info == (stmt_vec_info) 0x0
         |- return opt_result::success ();
         OR
         |- PURE_SLP_STMT (stmt_info) && !node then dump "handled only by SLP
analysis\n"
           |- Early return opt_result::success ();
         |- vectorizable_load/store/call_convert/... // Not Hit
       |- LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P &&
!LOOP_VINFO_MASKS(loop_vinfo).is_empty ()
         |- vect_verify_loop_lens (loop_vinfo)
           |- assert (VECTOR_MODE_P (loop_vinfo->vector_mode); // Hit assert
result in ICE

    Finally, the DImode in loop_vinfo will hit the assert (VECTOR_MODE_P
(mode))
    in vect_verify_loop_lens.  This patch would like to return false
    directly if the loop_vinfo has relevant mode like DImode for the ICE
    fix, but still may have mis-optimization for similar cases.  We will try
    to cover that in separated patches.

    The below test suites are passed for this patch.
    * The rv64gcv fully regression test.
    * The x86 bootstrap test.
    * The x86 fully regression test.

            PR middle-end/116351

    gcc/ChangeLog:

            * tree-vect-loop.cc (vect_verify_loop_lens): Return false if the
            loop_vinfo has relevant mode such as DImode.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr116351-1.c: New test.
            * gcc.target/riscv/rvv/base/pr116351-2.c: New test.
            * gcc.target/riscv/rvv/base/pr116351.h: New test.

    Signed-off-by: Pan Li <pan2...@intel.com>

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