https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118880
Georg-Johann Lay <gjl at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords|documentation, needs-source |missed-optimization
Resolution|--- |DUPLICATE
Status|WAITING |RESOLVED
--- Comment #4 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
I cannot reproduce that. With v14 head and -save-temps, the generated assembly
is:
__vector_7:
__gcc_isr 1
/* prologue: Signal */
/* frame size = 0 */
/* stack size = 0...4 */
.L__stack_usage = 0 + __gcc_isr.n_pushed
sts overflowState,__zero_reg__
cbi 0x17,0
.L3:
sbis 0x16,2
rjmp .L2
sbis 0x16,0
rjmp .L3
.L2:
ldi r24,lo8(-8)
sbic 0x16,0
ldi r24,lo8(-88)
.L11:
out 0xd,r24
ldi r24,lo8(-16)
out 0xe,r24
/* epilogue start */
__gcc_isr 2
reti
__gcc_isr 0,r24
so __gcc_isr is used as expected. This is resolved by gas to:
00000048 <__vector_7>:
48: 1f 92 push r1
4a: 1f b6 in r1, 0x3f ; 63
4c: 1f 92 push r1
4e: 11 24 eor r1, r1
50: 8f 93 push r24
52: 10 92 60 00 sts 0x0060, r1 ; 0x800060 <overflowState>
...
Since R1 is used to set overflowState, R1 has to be initialized, and CLR R1
clobbers SREG, so that must be saved, too. There is currently no way to
retroactively rewrite that code to use, say, LDI R24,0 to avoid clobbering SREG
and R1. There is curently no other way than inline assembly when your timing
constrainst are too tight for that code.
*** This bug has been marked as a duplicate of bug 115817 ***
