https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2025-02-04
            Summary|[15 Regression] GCC         |GCC generate illegal riscv
                   |generate illegal riscv      |instruction `vsetvli
                   |instruction `vsetvli        |zero,zero,e64,mf4,ta,ma`
                   |zero,zero,e64,mf4,ta,ma`    |with -O2 and -O3
                   |with -O2 and -O3            |
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #5 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Bisection to the commit that "fixed" this bug points to:

commit b82a5810e7bcc82b933e16f9067879b9d22b85c7
Author: Robin Dapp <rd...@ventanamicro.com>
Date:   Thu Nov 21 14:49:53 2024 +0100

    RISC-V: Ensure vtype for full-register moves [PR117544].

    As discussed in PR117544 the VTYPE register is not preserved across
    function calls.  Even though vmv1r-like instructions operate
    independently of the actual vtype they still require a valid vtype.  As
    we cannot guarantee that the vtype is valid we must make sure to emit a
    vsetvl between a function call and a vmv1r.v.

    This patch makes the necessary changes by splitting the full-reg-move
    insns into patterns that use the vtype register and adding vmov to the
    types of instructions requiring a vset.

            PR target/117544

    gcc/ChangeLog:

            * config/riscv/vector.md (*mov<mode>_whole): Split.
            (*mov<mode>_fract): Ditto.
            (*mov<mode>): Ditto.
            (*mov<mode>_vls): Ditto.
            (*mov<mode>_reg_whole_vtype): New pattern with vtype use.
            (*mov<mode>_fract_vtype): Ditto.
            (*mov<mode>_vtype): Ditto.
            (*mov<mode>_vls_vtype): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/abi-call-args-4.c: Expect vsetvl.
            * gcc.target/riscv/rvv/base/pr117544.c: New test.


But I strongly suspect that just made whatever the underlying issue is go
latent.  Conceptually that just makes us do vlen/vtype analysis on additional
instructions which could certainly perturb vsetvl generation.

I'm removing the regression marker since it's not triggering on the trunk. 
However, I'm leaving the bug open as I have no confidence it's actually fixed.

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