https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114442
--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:64a162d5562a333b816f6dc188814c14ba3c9f2c commit r15-7081-g64a162d5562a333b816f6dc188814c14ba3c9f2c Author: Jeff Law <j...@ventanamicro.com> Date: Mon Jan 20 14:50:57 2025 -0700 [PR target/114442] Add reservations for all insn types to xiangshan-nanhu model The RISC-V backend has checks to verify that every used insn has an associated type and that every insn type maps to some reservation in the DFA model. If either test fails we ICE. With the cpu/isa allowed to vary independently from the tune/scheduler model, it's entirely possible (in fact trivial) to trigger those kinds of ICEs. This patch "fixes" the ICEs for xiangshan-nanhu by throwing every unknown insn type into a special bucket I wouldn't be surprised if a few of them are implemented (like rotates as the chip seems to have other bitmanip extensions). But I know nothing about this design and the DFA author hasn't responded to requests to update the DFA in ~6 months. This should dramatically reduce the number of ICEs in the testsuite if someone were to turn on xiangshan-nanhu scheduling. Not strictly a regression, but a bugfix and highly isolated to the xiangshan-nanhu tuning in the RISC-V backend. So I'm gating this into gcc-15, assuming pre-commit doesn't balk. PR target/114442 gcc/ * config/riscv/xiangshan.md: Add missing insn types to a new dummy insn reservation. gcc/testsuite * gcc.target/riscv/pr114442.c: New test.
