https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118512
--- Comment #10 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Eric Botcazou <ebotca...@gcc.gnu.org>: https://gcc.gnu.org/g:d309844d6fe02e695eb82cbd30fd135e836f24eb commit r15-7023-gd309844d6fe02e695eb82cbd30fd135e836f24eb Author: Eric Botcazou <ebotca...@adacore.com> Date: Sat Jan 18 18:58:02 2025 +0100 Fix bootstrap failure on SPARC with -O3 -mcpu=niagara4 This is a regression present on the mainline only, but the underlying issue has been latent for years: the compiler and the assembler disagree on the support of the VIS 3B SIMD ISA, the former bundling it with VIS 3 but not the latter. IMO the documentation is not very clear, so this patch just aligns the compiler with the assembler. gcc/ PR target/118512 * config/sparc/sparc-c.cc (sparc_target_macros): Deal with VIS 3B. * config/sparc/sparc.cc (dump_target_flag_bits): Likewise. (sparc_option_override): Likewise. (sparc_vis_init_builtins): Likewise. * config/sparc/sparc.md (fpcmp_vis): Replace TARGET_VIS3 with TARGET_VIS3B. (vec_cmp): Likewise. (fpcmpu_vis): Likewise. (vec_cmpu): Likewise. (vcond_mask_): Likewise. * config/sparc/sparc.opt (VIS3B): New target mask. * doc/invoke.texi (SPARC options): Document -mvis3b. gcc/testsuite/ * gcc.target/sparc/20230328-1.c: Pass -mvis3b instead of -mvis3. * gcc.target/sparc/20230328-4.c: Likewise. * gcc.target/sparc/fucmp.c: Likewise. * gcc.target/sparc/vis3misc.c: Likewise.
