https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118446
Bug ID: 118446
Summary: __builtin_iseqsig does not raise exception when
supplied with NaN on Cortex-M at -O1 or higher
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: azoff at gcc dot gnu.org
Target Milestone: ---
Consider the following function (extracted from
gcc.dg/torture/builtin-iseqsig-1.c):
#include <fenv.h>
void
ffalse (float x, float y)
{
if (__builtin_iseqsig (x, y))
__builtin_abort ();
}
The combine step, for the above snippet, incorrectly selects cmpsf_vfp instead
of cmpsf_trap_vfp at -O1 or higher. As a consequence, no exception is raised
when one of the input values are NaN.
Snippet from foo.c.302r.combine:
Trying 7 -> 11:
7: cc:CCFPE=cmp(r117:SF,r118:SF)
11: cc:CCFPE=cc:CCFPE
Successfully matched this instruction:
(set (reg:CCFP 100 cc)
(compare:CCFP (reg/v:SF 117 [ x ])
(reg/v:SF 118 [ y ])))
Successfully matched this instruction:
(set (pc)
(if_then_else (unlt (reg:CCFP 100 cc)
(const_int 0 [0]))
(label_ref:SI 24)
(pc)))
allowing combination of insns 7 and 11
original costs 4 + 2 = 22
replacement cost 20
deferring deletion of insn with uid = 7.
modifying other_insn 12: pc={(unlt(cc:CCFP,0))?L24:pc}
REG_DEAD cc:CC
REG_BR_PROB 536870916
deferring rescan insn with uid = 12.
modifying insn i3 11: cc:CCFP=cmp(r117:SF,r118:SF)
deferring rescan insn with uid = 11.
I see the above issue for Cortex-M4/7/33/55/85 with -mfloat-abi=hard.
Example command line to reproduce:
arm-none-eabi-gcc -march=armv7e-m+fp -mfloat-abi=hard -mfpu=auto -O1 -S -o -
foo.c
