https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118342
--- Comment #13 from Mayshao-oc at zhaoxin dot com --- (In reply to Jakub Jelinek from comment #4) > Well, there is also the > "On some older processors, use of a 32-bit operand size may clear the upper > 32 bits of a 64-bit destination while leaving the lower 32 bits unmodified." > footnote in the Intel manual. So we can use it for 64 value or perhaps > others which have the upper 32 bits clear, but not say for -1. I test the following code on the oldest platform in Zhaoxin: mov $0xffffffffffffffff,%rdi xor %rax, %rax bsf %eax, %edi mov %rdi, %rax ret bsf will not clear upper 32bit of rdi.At the same time, I ask my colleague to check in perspective of hardware. He confirms that no matter which operand size for the bsf instruction, if the source register is zero, the destination register will not be changed, and the upper 32 bits clear dose not exist in Zhaoxin processor.
