[Bug target/118137] riscv64: sub-word atomic OR with -1 affects surrounding bytes

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118137

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <l...@gcc.gnu.org>:

https://gcc.gnu.org/g:013e66ea95a241c472b9d87430efaf6c759cf5c0

commit r15-6668-g013e66ea95a241c472b9d87430efaf6c759cf5c0
Author: Andreas Schwab <sch...@suse.de>
Date:   Tue Jan 7 12:23:37 2025 -0700

    [PATCH] riscv: add mising masking in lrsc expander (PR118137)

    gcc:
            PR target/118137
            * config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
            to shifted value.

    gcc/testsuite:
            PR target/118137
            * gcc.dg/atomic/pr118137.c: New.