[Bug target/96342] [SVE] Add support for "omp declare simd"

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96342

--- Comment #20 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>:

https://gcc.gnu.org/g:830bead4859cd00da87e1304ba249cf0d3eb5a5a

commit r15-6597-g830bead4859cd00da87e1304ba249cf0d3eb5a5a
Author: Tamar Christina <tamar.christ...@arm.com>
Date:   Mon Jan 6 09:24:36 2025 +0000

    AArch64: Implement four and eight chunk VLA concats [PR118272]

    The following testcase

      #pragma GCC target ("+sve")
      extern char __attribute__ ((simd, const)) fn3 (int, short);
      void test_fn3 (float *a, float *b, double *c, int n)
      {
        for (int i = 0; i < n; ++i)
          a[i] = fn3 (b[i], c[i]);
      }

    at -Ofast ICEs because my previous patch only added support for combining 2
    partial SVE vectors into a bigger vector.  However There can also 4 and 8
    piece subvectors.

    This patch fixes this by implementing the missing expansions.

    gcc/ChangeLog:

            PR target/96342
            PR target/118272
            * config/aarch64/aarch64-sve.md (vec_init<mode><Vquad>,
            vec_initvnx16qivnx2qi): New.
            * config/aarch64/aarch64.cc
(aarch64_sve_expand_vector_init_subvector):
            Rewrite to support any arbitrary combinations.
            * config/aarch64/iterators.md (SVE_NO2E): Update to use SVE_NO4E
            (SVE_NO2E, Vquad): New.

    gcc/testsuite/ChangeLog:

            PR target/96342
            PR target/118272
            * gcc.target/aarch64/vect-simd-clone-3.c: New test.