[Bug target/118017] [15 Regression] ICE: maximum number of generated reload insns per insn achieved (90) with -Og -frounding-math -mno-80387 -mno-mmx

[ubizjak at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118017

--- Comment #4 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Uroš Bizjak from comment #3)
> It looks to me that reload is trying to handle the following sequence from
> _.322r.ira dump:
> 
> (insn 32 31 35 2 (set (subreg:TI (reg:TD 99 [ _2 ]) 0)
>         (reg:TI 20 xmm0)) "pr118017.c":14:24 94 {*movti_internal}
>      (expr_list:REG_DEAD (reg:TI 20 xmm0)
>         (nil)))
> ...
> 
> (insn 41 40 42 2 (set (mem/c:TI (plus:DI (reg/f:DI 19 frame)
>                 (const_int -240 [0xffffffffffffff10])) [0  S16 A128])
>         (subreg:TI (reg:TD 99 [ _2 ]) 0)) "pr118017.c":14:20 94
> {*movti_internal}
>      (nil))

Please note that TImode and TDmode are tieable on x86_64 targets, so LRA should
simple consider all registers as TImode:

#define VALID_SSE_REG_MODE(MODE)                                        \
  ((MODE) == V1TImode || (MODE) == TImode                               \
   || (MODE) == V4SFmode || (MODE) == V4SImode                          \
   || (MODE) == SFmode || (MODE) == SImode                              \
   || (MODE) == TFmode || (MODE) == TDmode)

and in ix86_modes_tieable_p:

  /* If MODE2 is only appropriate for an SSE register, then tie with
     any other mode acceptable to SSE registers.  */
  ...
  if (GET_MODE_SIZE (mode2) == 16
      && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
    return (GET_MODE_SIZE (mode1) == 16
            && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));