[Bug target/117562] [15 Regression] 40% slowdown of 482.sphinx3 on Zen4, Zen5 since r15-5120-g9a62c149589103

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117562

--- Comment #12 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuho...@gcc.gnu.org>:

https://gcc.gnu.org/g:ba4cf2e296d8d5950c3d356fa6b6efcad00d0189

commit r15-5639-gba4cf2e296d8d5950c3d356fa6b6efcad00d0189
Author: liuhongt <hongtao....@intel.com>
Date:   Thu Nov 21 23:57:38 2024 -0800

    Fix uninitialized operands[2] in vec_unpacks_hi_v4sf.

    It could cause weired spill in RA when register pressure is high.

    gcc/ChangeLog:

            PR target/117562
            * config/i386/sse.md (vec_unpacks_hi_v4sf): Initialize
            operands[2] with CONST0_RTX.