https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117690
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jeff Law <l...@gcc.gnu.org>: https://gcc.gnu.org/g:9b7917b34fa54d5b4ff0094ef4d949c6ac50f02e commit r15-5578-g9b7917b34fa54d5b4ff0094ef4d949c6ac50f02e Author: Jeff Law <j...@ventanamicro.com> Date: Thu Nov 21 16:21:07 2024 -0700 [RISC-V][PR target/117690] Add missing shift in constant synthesis As hinted out in the BZ, we were missing a left shift in the constant synthesis in the case where the upper 32 bits can be synthesized using a shNadd of the low 32 bits. This adjusts the synthesis to add the missing left shift and adjusts the cost to account for the additional instruction. Regression tested on riscv64-elf in my tester. Waiting for the pre-commit tester before moving forward. PR target/117690 gcc/ * config/riscv/riscv.cc (riscv_build_integer): Add missing left shift when using shNadd to derive upper 32 bits from lower 32 bits. gcc/testsuite * gcc.target/riscv/pr117690.c: New test. * gcc.target/riscv/synthesis-13.c: Adjust expected output.
