[Bug target/115336] [15] rv64gcv_zvl256b miscompile at -O3

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rd...@gcc.gnu.org>:

https://gcc.gnu.org/g:b89273a049a76ffc29dd43a536ad329f0d994c05

commit r15-5389-gb89273a049a76ffc29dd43a536ad329f0d994c05
Author: Robin Dapp <rd...@ventanamicro.com>
Date:   Thu Aug 8 10:31:22 2024 +0200

    RISC-V: Add else operand to masked loads [PR115336].

    This patch adds else operands to masked loads.  Currently the default
    else operand predicate just accepts "undefined" (i.e. SCRATCH) values.

            PR middle-end/115336
            PR middle-end/116059

    gcc/ChangeLog:

            * config/riscv/autovec.md: Add else operand.
            * config/riscv/predicates.md (maskload_else_operand): New
            predicate.
            * config/riscv/riscv-v.cc (get_else_operand): Remove static.
            (expand_load_store): Use get_else_operand and adjust index.
            (expand_gather_scatter): Ditto.
            (expand_lanes_load_store): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr115336.c: New test.
            * gcc.target/riscv/rvv/autovec/pr116059.c: New test.