https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117566
Bug ID: 117566
Summary: RISC-V: Enable VLS tests in testsuite for various
targets
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: rdapp at gcc dot gnu.org
CC: ewlu at rivosinc dot com, kito.cheng at gmail dot com,
law at gcc dot gnu.org, palmer at dabbelt dot com,
patrick at rivosinc dot com, vineetg at rivosinc dot com
Target Milestone: ---
Target: riscv
Not a typical bug either, more of a reminder and potential placeholder for
stage 3.
Right now the VLS tests in our test suite are compiled with -march=rv64gcv
-mrvv-vector-bits=zvl. This means that they are compiled for 128-bit vector
targets and will obviously (runtime) fail on all others.
It's (mostly) not the tests themselves which are problematic but that we rely
on the 128-bit vector length. The tests would pass on other zvls if we just
compiled them differently.
The way I see it we have two options:
(1) Disable the tests for everything except zvl128b.
(2) Duplicate all tests for common zvls.
(3) Dynamically modify the -march according to the current target under test.
What we already have is target checks for common zvls like
check_effective_target_rvv_zvl256b_ok. Those would allow implementing (1)
easily.
For (3) we'd need to query the current target and then build an -march string
for just the affected tests that amends the -march string provided by the test
harness. This is not strictly how tests are supposed to work AFAIK as we
usually just disable those that the current target doesn't support. I think,
however, that we could increase our test coverage significantly by deviating
from this rule a bit - all tests should work on every zvl >= 128b.
