https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117353
--- Comment #2 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
For other benign instances of the pattern lshrv8qi3, typically it goes through
a splitter in autovec.md which converts it into the canonical RVV form with all
the VL info.
(define_insn_and_split "<optab><mode>3"
[(set (match_operand:V_VLSI 0 "register_operand" "=vr")
(any_shift:V_VLSI
(match_operand:V_VLSI 1 "register_operand" " vr")
(match_operand:<VEL> 2 "vector_scalar_shift_operand" " rK")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
operands[2] = gen_lowpart (Pmode, operands[2]);
riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
However in the failure case it is introduced late by reload and thus is not
getting split as intended.
116: r173:V8QI=r223:V8QI
REG_DEAD r222:V8QI
Inserting insn reload before:
117: r224:V8QI={(unspec[const_vector,0x8,0x2,0x2,0x2,vl:SI,vtype:SI]
87)?vec_series(0,0x1):unspec[zero:DI] 86}
118: r225:V8QI=r224:V8QI 0>>0x1
119: r226:V8QI=r225:V8QI
120: r227:V8QI=[const(`*.LANCHOR0'+0x8)]
REG_EQUAL const_vector
121: r223:V8QI={(unspec[const_vector,0x8,0x2,0x2,0x2,vl:SI,vtype:SI]
87)?r226:V8QI+r227:V8QI:unspec[zero:DI] 86}
REG_EQUAL const_vector
Considering alt=0 of insn 117: (0) =vd (1) vm (2) vu (3) rK (4)
i (5) i (6) i
0 Non pseudo reload: reject++
1 Non-pseudo reload: reject+=2
1 Small class reload: reject+=3
1 Non input pseudo reload: reject++
overall=13,losers=1,rld_nregs=1
Considering alt=1 of insn 117: (0) vd (1) vm (2) 0 (3) rK (4) i
(5) i (6) i
0 Non pseudo reload: reject++
1 Non-pseudo reload: reject+=2
1 Small class reload: reject+=3
1 Non input pseudo reload: reject++
2 Matching alt: reject+=2
2 Non-pseudo reload: reject+=2
2 Non input pseudo reload: reject++
overall=30,losers=3 -- refuse
Considering alt=2 of insn 117: (0) vr (1) Wc1 (2) vu (3) rK (4)
i (5) i (6) i
0 Non pseudo reload: reject++
overall=1,losers=0,rld_nregs=0
Choosing alt 2 in insn 117: (0) vr (1) Wc1 (2) vu (3) rK (4) i (5)
i (6) i {pred_seriesv8qi}
Change to class V_REGS for r224
Considering alt=0 of insn 118: (0) =vr (1) vr (2) rK
0 Non pseudo reload: reject++
1 Non pseudo reload: reject++
overall=2,losers=0,rld_nregs=0
Choosing alt 0 in insn 118: (0) =vr (1) vr (2) rK {lshrv8qi3}
Change to class V_REGS for r225
Creating newreg=228, assigning class GR_REGS to addr r228
Considering alt=0 of insn 120: (0) =vr (1) m
0 Non pseudo reload: reject++
overall=1,losers=0,rld_nregs=0
Choosing alt 0 in insn 120: (0) =vr (1) m {*movv8qi}
Change to class V_REGS for r227
