https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115905
Eric Botcazou <ebotcazou at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |ebotcazou at gcc dot gnu.org
--- Comment #15 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
The symptom on 64-bit SPARC is that MEM_ALIGN is applied to something that is
not a MEM, but a PARALLEL:
(parallel:DI [
(expr_list:REG_DEP_TRUE (reg:DI 114 [ <retval> ])
(const_int 0 [0]))
])
This comes from the Early SRA pass which turns:
D.8652.D.8175._M_fr_ptr = _11;
<retval> = D.8652;
into
SR.40_20 = _11;
MEM[(struct Handle *)&<retval>] = SR.40_20;
which is a store to something that is not addressable at the RTL level.
