https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112600
--- Comment #20 from Li Pan <pan2.li at intel dot com> --- (In reply to Li Pan from comment #19) > interesting, I will take a look for f2 after some more sat_* supported. RISC-V backend works well for all of above pattern but x86 failed on f2, let me dig more details for this.
