https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #325 from Kazumoto Kojima <kkojima at gcc dot gnu.org> ---
(In reply to John Paul Adrian Glaubitz from comment #319)
> Created attachment 59188 [details]
> Preprocessed source from from comment #318
Thanks for the test case and other comments. I can reproduce the ICE with
cross gnat1. From the rtl dumps, it seems
* A complex valued function returns SCmode value in fr0 and fr1 pair.
* The real/imaginary part of this value is moved to the SFmode reg.
(insn 105 104 106 16 (parallel [
(set (reg:SF 184 [ _24 ])
(subreg:SF (reg:SC 241) 0))
(use (reg:SI 154 fpscr0))
]) "a-ngcefu.adb":164:17 -1
(nil))
* subreg1 pass splits this multiword subreg to single word subreg but with
SImode reg.
(insn 103 101 104 10 (parallel [
(set (subreg:SF (reg:SI 344) 0)
(reg:SF 64 fr0))
(use (reg:SI 154 fpscr0))
]) "a-ngcefu.adb":164:17 222 {movsf_ie_ra}
(expr_list:REG_DEAD (reg:SF 64 fr0)
(nil)))
...
(insn 105 104 106 10 (parallel [
(set (reg:SF 184 [ _24 ])
(subreg:SF (reg:SI 344) 0))
(use (reg:SI 154 fpscr0))
]) "a-ngcefu.adb":164:17 222 {movsf_ie_ra}
(expr_list:REG_DEAD (reg:SI 344)
(nil)))
Our movsf logic for LRA doesn't handle these well. If these reg from/to subreg
of SImode move is splitted with fpul, it will cause some very bad code or ICE.
