https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212
--- Comment #302 from Kazumoto Kojima <kkojima at gcc dot gnu.org> ---
(In reply to Oleg Endo from comment #300)
> (In reply to Kazumoto Kojima from comment #297)
> >
> > > > && REG_P (operands[2]) && REGNO (operands[2]) == R4_REG
> > > > && REG_P (operands[3]) && REGNO (operands[3]) == R5_REG
> > > > && REG_P (operands[4]) && REGNO (operands[4]) == R6_REG"
> > >
> > > Out of curiousity, why are these checks needed?
> >
> > Otherwise, operands[2-4] can be replaced by another register. I've seen that
> > in some cases.
>
> So the checks fail the pattern match unless all hard regs are in place and
> so if something tries to change the reg operands in the insn it will fail
> and will stay put? Is that what's happening there?
Yes, that's what I suppose. If the operands of that pattern match with another
registers, the instruction with the operands[2-4] other than r4-r6 would be
recognizable.
I'm not sure if my memory is correct, but such rewriting was attempted and
succeeded at the RA or post reload stage.
Another way would be to define a predicate sfunc_arg[012]_reg which matches
r[456] only and use it in match_operand to avoid unexpected matching.
(define_insn "block_lump_real_i4"
[(set (mem:BLK (match_operand:SI 2 "sfunc_arg0_reg" "=r,r"))
(mem:BLK (match_operand:SI 3 "sfunc_arg1_reg" "=r,r")))
(use (match_operand:SI 0 "arith_reg_operand" "r,r"))
(use (match_operand 1 "" "Z,Ccl"))
(use (match_operand:SI 4 "sfunc_arg2_reg" "=r,r"))
...
(clobber (reg:SI R3_REG))]
"TARGET_HARD_SH4"
...
It also worked for me.
