https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116778
Bug ID: 116778
Summary: [lra][avr] Wrong code with -mlra (bitfld-lra.c)
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: gjl at gcc dot gnu.org
Target Milestone: ---
Created attachment 59145
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=59145&action=edit
bitfld-lra.c: C test case
$ avr-gcc -mmcu=atmega128 -dumpbase "" -save-temps -dp -Os -mlra bitfld-lra.c
-o bitfld-lra.elf
produces wrong code for the attached test case
struct
{
unsigned long long u33 : 33;
unsigned long long u40 : 40;
unsigned long long u41 : 41;
} a = { 0x100000, 0, 0x100000 }, b = { 1LL << 32, 0, 0 };
long long f = 1LL << 32, g = 1LL << 32;
int main (void)
{
if (a.u33 * a.u33 != 0 || a.u33 * a.u40 * a.u33 != 0
|| a.u41 * a.u33 != 1LL << 40)
__builtin_abort();
if (b.u33 + g != 1LL << 33 || b.u33 + f != 1LL << 33 || g + g != 1LL << 33)
__builtin_abort();
}
For the first addition "b.u33 + g != 1LL << 33" the asm reads something like
ldd r13,Y+1 ; 660 [c=4 l=1] movqi_insn/3
mov r14,r13 ; 661 [c=4 l=1] movqi_insn/0
lds r15,g+5 ; 662 [c=4 l=2] movqi_insn/3
lds r16,g+6 ; 663 [c=4 l=2] movqi_insn/3
lds r17,g+7 ; 664 [c=4 l=2] movqi_insn/3
call __adddi3 ; 665 [c=32 l=2] *adddi3_insn
where __adddi3 performs R10[8] + R18[8]. However, R13 has a wrong value of
0x01 due to the load insns 660 and 661 so that the value in R10[8] is
0x0101000000 instead of 0x0100000000 when __adddi3 is called.
Target: avr
Configured with: ../../source/gcc-master/configure --target=avr --disable-nls
--with-dwarf2 --with-gnu-as --with-gnu-ld --disable-shared
--enable-languages=c,c++
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 15.0.0 20240918 (experimental) (GCC)
