[Bug tree-optimization/116628] [15 Regression] ICE in vect_analyze_loop_1 on aarch64 with -Ofast in TSVC

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116628

--- Comment #7 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>:

https://gcc.gnu.org/g:2c4438d39156493b5b382eb48b1f884ca5ab7ed4

commit r15-3518-g2c4438d39156493b5b382eb48b1f884ca5ab7ed4
Author: Tamar Christina <tamar.christ...@arm.com>
Date:   Fri Sep 6 14:05:43 2024 +0100

    middle-end: check that the lhs of a COND_EXPR is an SSA_NAME in cond_store
recognition [PR116628]

    Because the vect_recog_bool_pattern can at the moment still transition
    out of GIMPLE and back into GENERIC the vect_recog_cond_store_pattern can
    end up using an expression as a mask rather than an SSA_NAME.

    This adds an explicit check that we have a mask and not an expression.

    gcc/ChangeLog:

            PR tree-optimization/116628
            * tree-vect-patterns.cc (vect_recog_cond_store_pattern): Add
SSA_NAME
            check on expression.

    gcc/testsuite/ChangeLog:

            PR tree-optimization/116628
            * gcc.dg/vect/pr116628.c: New test.