[Bug target/116466] The standard instruction pattern of RISC-V addv has generated an unnecessary instruction.

[law at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116466

--- Comment #2 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Looking at this, I would fully expect that in an optimizing compilation that
the redundant extension would be eliminated.   Are you seeing the redundant
sign extensions in the final assembly output or just in the intermediate RTL?

If the former, can you attach a testcase?

Thanks.