https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116229
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>: https://gcc.gnu.org/g:2c24e0568392e51a77ebdaab629d631969ce8966 commit r15-2839-g2c24e0568392e51a77ebdaab629d631969ce8966 Author: Tamar Christina <tamar.christ...@arm.com> Date: Thu Aug 8 18:51:30 2024 +0100 AArch64: Fix signbit mask creation after late combine [PR116229] The optimization to generate a Di signbit constant by using fneg was relying on nothing being able to push the constant into the negate. It's run quite late for this reason. However late combine now runs after it and triggers RTL simplification based on the neg. When -fno-signed-zeros this ends up dropping the - from the -0.0 and thus producing incorrect code. This change adds a new unspec FNEG on DI mode which prevents this simplication. gcc/ChangeLog: PR target/116229 * config/aarch64/aarch64-simd.md (aarch64_fnegv2di2<vczle><vczbe>): New. * config/aarch64/aarch64.cc (aarch64_maybe_generate_simd_constant): Update call to gen_aarch64_fnegv2di2. * config/aarch64/iterators.md: New UNSPEC_FNEG. gcc/testsuite/ChangeLog: PR target/116229 * gcc.target/aarch64/pr116229.c: New test.
