https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115969
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Component|rtl-optimization |target
--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(define_insn "*aarch64_simd_ld1r<mode>"
[(set (match_operand:VALLS_F16 0 "register_operand" "=w")
(vec_duplicate:VALLS_F16
(match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))]
"TARGET_SIMD"
"ld1r\\t{%0.<Vtype>}, %1"
[(set_attr "type" "neon_load1_all_lanes")]
)
(define_predicate "aarch64_simd_struct_operand"
(and (match_code "mem")
(match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
(define_memory_constraint "Utv"
"@internal
An address valid for loading/storing opaque structure
types wider than TImode."
(and (match_code "mem")
(match_test "aarch64_simd_mem_operand_p (op)")))
The problem is here:
```
/* Return TRUE if OP is a valid vector addressing mode. */
bool
aarch64_simd_mem_operand_p (rtx op)
{
return MEM_P (op) && (GET_CODE (XEXP (op, 0)) == POST_INC
|| REG_P (XEXP (op, 0)));
}
```
It does not check the mem address to be correct..
