https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688
--- Comment #38 from Mayshao-oc at zhaoxin dot com --- vmovdqu is also atomic in Zhaoxin processors if it meets three requirements: 1. the address of its memory operand must be 16-byte aligned 2. vmovdqu is vex.128 not vex.256 3. the memory type of the address is WB (In reply to Richard Henderson from comment #36) > (In reply to Mayshao-oc from comment #34) > > (In reply to Jakub Jelinek from comment #17) > > > Fixed for AMD on the library side too. > > > We need a statement from Zhaoxin and VIA for their CPUs. > > > > Sorry for the late reply. > > We guarantee that VMOVDQA will be an atomic load or store provided 128 bit > > aligned address in Zhaoxin processors, provided that the memory type is WB. > > Can we extend this patch to Zhaoxin processors as well? > > Is VMOVDQU atomic, provided the address is aligned in Zhaoxin processors? > > In QEMU, we make use of this additional guarantee from AMD. > We also reference this gcc bugzilla entry for documentation. :-) (In reply to Richard Henderson from comment #36) > (In reply to Mayshao-oc from comment #34) > > (In reply to Jakub Jelinek from comment #17) > > > Fixed for AMD on the library side too. > > > We need a statement from Zhaoxin and VIA for their CPUs. > > > > Sorry for the late reply. > > We guarantee that VMOVDQA will be an atomic load or store provided 128 bit > > aligned address in Zhaoxin processors, provided that the memory type is WB. > > Can we extend this patch to Zhaoxin processors as well? > > Is VMOVDQU atomic, provided the address is aligned in Zhaoxin processors? > > In QEMU, we make use of this additional guarantee from AMD. > We also reference this gcc bugzilla entry for documentation. :-)
