https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115901
--- Comment #9 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
```
trying to combine definition of r63 in:
21: v31:DI=x0:DI
into:
22: v30:V2DI=v31:V2DI
successfully matched this instruction to *aarch64_simd_movv2di:
(set (reg:V2DI 62 v30 [orig:106 _3 ] [106])
(reg:V2DI 0 x0 [orig:101 _2 ] [101]))
original cost = 4 + 4 (weighted: 8.000000), replacement cost = 4 (weighted:
4.000000); keeping replacement
rescanning insn with uid = 22.
updating insn 22 in-place
verify found no changes in insn with uid = 22.
deleting insn 21
deleting insn with uid = 21.
```
// For now, we only support inferring uses of mem.
gcc_assert (regno == MEM_REGNO);
I am not sure but the other use of x0 was via the call and the definition was
from:
(insn 8 6 21 2 (set (reg:DI 0 x0 [orig:101 _2 ] [101])
(sign_extend:DI (mem/c:SI (lo_sum:DI (reg/f:DI 0 x0 [105])
(symbol_ref:DI ("*.LANCHOR0") [flags 0x182])) [1 pD.4414+0
S4 A32]))) "/app/example.cpp":9:15 105 {*extendsidi2_aarch64}
(nil))
So recap before late_combine2 we had:
```
(insn 21 8 22 2 (set (reg:DI 63 v31 [orig:101 _2 ] [101])
(reg:DI 0 x0 [orig:101 _2 ] [101])) "/app/example.cpp":9:15 70
{*movdi_aarch64}
(nil))
(insn 22 21 10 2 (set (reg:V2DI 62 v30 [orig:106 _3 ] [106])
(reg:V2DI 63 v31 [orig:101 _2 ] [101])) "/app/example.cpp":9:15 1271
{*aarch64_simd_movv2di}
(nil))
(insn 10 22 11 2 (set (reg:V2DI 62 v30 [orig:106 _3 ] [106])
(vec_merge:V2DI (const_vector:V2DI [
(const_int 0 [0]) repeated x2
])
(reg:V2DI 62 v30 [orig:106 _3 ] [106])
(const_int 2 [0x2]))) "/app/example.cpp":9:15 1814
{aarch64_simd_vec_set_zerov2di}
(expr_list:REG_EQUIV (mem/c:V2DI (plus:DI (reg/f:DI 64 sfp)
(const_int -16 [0xfffffffffffffff0])) [2 invD.4422+0 S16 A128])
(nil)))
```
Which was generated from:
```
(insn 10 8 11 2 (set (reg:V2DI 106 [ _3 ])
(vec_merge:V2DI (const_vector:V2DI [
(const_int 0 [0]) repeated x2
])
(subreg:V2DI (reg:DI 101 [ _2 ]) 0)
(const_int 2 [0x2]))) "/app/example.cpp":9:15 1814
{aarch64_simd_vec_set_zerov2di}
(expr_list:REG_EQUIV (mem/c:V2DI (plus:DI (reg/f:DI 64 sfp)
(const_int -16 [0xfffffffffffffff0])) [2 invD.4422+0 S16 A128])
(nil)))
```
before RA.
Note There is a missing optimization which transform:
```
(insn 10 8 11 2 (set (reg:V2DI 106 [ _3 ])
(vec_merge:V2DI (const_vector:V2DI [
(const_int 0 [0]) repeated x2
])
(subreg:V2DI (reg:DI 101 [ _2 ]) 0)
(const_int 2 [0x2]))) "/app/example.cpp":9:15 1814
{aarch64_simd_vec_set_zerov2di}
(expr_list:REG_EQUIV (mem/c:V2DI (plus:DI (reg/f:DI 64 sfp)
(const_int -16 [0xfffffffffffffff0])) [2 invD.4422+0 S16 A128])
(nil)))
```
into:
```
(insn 9 11 10 2 (set (reg:V2DI 63 v31)
(vec_concat:V2DI (reg:DI 101 [ _2 ])
(const_int 0 [0]))) "/app/example.cpp":9:15 2966
{*aarch64_combinezdi}
(expr_list:REG_DEAD (reg:DI 101 [ _2 ])
(nil)))
```
But that is a different story (though it would workaround the ICE here and in
the original testcase).
