[Bug rtl-optimization/115862] [15 Regression] RISC-V: ICE during RTL combine pass in malloc.c for zvl512b and zvl1024b

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115862

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Li Xu <x...@gcc.gnu.org>:

https://gcc.gnu.org/g:63d7d5998e3768f6e3703c29e8774e8b54af108c

commit r15-1993-g63d7d5998e3768f6e3703c29e8774e8b54af108c
Author: xuli <xu...@eswincomputing.com>
Date:   Thu Jul 11 04:29:11 2024 +0000

    RISC-V: Disable misaligned vector access in hook
riscv_slow_unaligned_access[PR115862]

    The reason is that in the following code, icode = movmisalignv8si has
    already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
    allowed by targetm.slow_unaligned_access,which is contradictory.

    (((icode = optab_handler (movmisalign_optab, mode))
               != CODE_FOR_nothing)
              || targetm.slow_unaligned_access (mode, align))

    misaligned vector access should be enabled by -mno-vector-strict-align
option.

            PR target/115862

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable
vector misalign.

    Signed-off-by: Li Xu <xu...@eswincomputing.com>