[Bug target/115881] [15 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1934 with -O2 -mx32 -maddress-mode=long

[ubizjak at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115881

Uroš Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2024-07-11
   Target Milestone|---                         |15.0
     Ever confirmed|0                           |1

--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
Confirmed, _late_combine2 is doing:

trying to combine definition of r1 in:
    6: {dx:DI=sp:DI+0xc;clobber flags:CC;}
      REG_EQUIV frame:DI-0x4
into:
   46: cx:DI=dx:DI
successfully matched this instruction to *leadi:
(set (reg:DI 2 cx [118])
    (plus:DI (reg/f:DI 7 sp)
        (const_int 12 [0xc])))
   31: {di:DI=zero_extend(dx:SI+0x1);clobber flags:CC;}
successfully matched this instruction to addsi_1_zext:
(parallel [
        (set (reg:DI 5 di)
            (zero_extend:DI (plus:SI (subreg:SI (reg/f:DI 7 sp) 0)
                    (const_int 13 [0xd]))))
        (clobber (reg:CC 17 flags))
    ])

which then triggers:

(define_peephole2
  [(set (match_operand:DI 0 "register_operand")
        (zero_extend:DI
          (plus:SI (match_operand:SI 1 "nonmemory_operand")
                   (match_operand:SI 2 "register_operand"))))]
  "TARGET_64BIT && !TARGET_OPT_AGU
   && REGNO (operands[0]) == REGNO (operands[2])
   && peep2_regno_dead_p (0, FLAGS_REG)"
  [(parallel [(set (match_dup 0)
                   (zero_extend:DI (plus:SI (match_dup 2) (match_dup 1))))
              (clobber (reg:CC FLAGS_REG))])])

However, there should be no SUBREG RTXes after reload.