https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725
Bug ID: 115725
Summary: RISC-V: Use wrong AVL for rv64gcv_zfh_zvl512b
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: sh.chiang04 at gmail dot com
CC: juzhe.zhong at rivai dot ai, kito at gcc dot gnu.org,
pan2.li at intel dot com, rdapp at gcc dot gnu.org
Target Milestone: ---
The fail test is extract from
gcc.target/riscv/rvv/autovec/vls-vlmax/test-vec_set.c (fail item is "T
(int16_t, vnx8hi, 0)")
compile option: -mabi=lp64d -march=rv64imafdcv_zfh_zvl512b -mcmodel=medlow
-ftree-vectorize -mrvv-vector-bits=zvl -O1 -std=c99
testcase:
#include <stdint-gcc.h>
#include <stdlib.h>
typedef int16_t vnx8hi __attribute__((vector_size (16)));
vnx8hi __attribute__((noipa))
vec_set_vnx8hi_0 (vnx8hi v, int16_t s)
{
v[0] = s;
return v;
}
int main ()
{
vnx8hi v, res;
v[1] = 1;
res = vec_set_vnx8hi_0 (v, 77);
if (res[1] != 1)
abort();
else
exit(0);
}
The first vsetivli in vec_set_vnx8hi_0, only use AVL= 1 and ta,ma for v[0] = s.
So the res[0] = 77, and res[1] may not be the same as v[1]. In main(), checking
(res[1] != 1) will get abort(). But -march with zvl128b is correct.
Assembly:
vec_set_vnx8hi_0:
vsetivli zero,1,e16,mf4,ta,ma
vle16.v v1,0(a1)
vmv.s.x v1,a2
vsetivli zero,8,e16,mf4,ta,ma
vse16.v v1,0(a0)
ret
main:
addi sp,sp,-48
sd ra,40(sp)
sd s0,32(sp)
addi s0,sp,16
vsetivli zero,2,e16,mf4,ta,ma
vmv.v.i v2,1
vsetivli zero,8,e16,mf4,ta,ma
vmv.v.i v1,0
vsetivli zero,2,e16,mf4,tu,ma
vslideup.vi v1,v2,1
mv a1,sp
vsetivli zero,8,e16,mf4,ta,ma
vse16.v v1,0(sp)
li a2,77
mv a0,s0
call vec_set_vnx8hi_0
vsetivli zero,8,e16,mf4,ta,ma
vle16.v v1,0(s0)
vslidedown.vi v1,v1,1
vmv.x.s a4,v1
li a5,1
bne a4,a5,.L5
li a0,0
call exit
.L5:
call abort
After avlprop pass AVL value is 1, more information for avlprop pass:
AVL propagation type: vlmax_ta
(insn 5 4 23 2 (set (reg/v:RVVMF4HI 137 [ v ])
(if_then_else:RVVMF4HI (unspec:RVVMF64BI [
(const_vector:RVVMF64BI [
(const_int 1 [0x1]) repeated x8
])
(reg:DI 138)
(const_int 2 [0x2]) repeated x2
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem/c:RVVMF4HI (reg:DI 144) [1 v+0 S16 A128])
(unspec:RVVMF4HI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "vsetvl.c":8:1 3450 {*pred_movrvvmf4hi}
(expr_list:REG_DEAD (reg:DI 144)
(nil)))
Number of successful AVL propagations: 1
Propagating AVL: (const_int 1 [0x1])
into: (insn 5 4 23 2 (set (reg/v:RVVMF4HI 137 [ v ])
(if_then_else:RVVMF4HI (unspec:RVVMF64BI [
(const_vector:RVVMF64BI [
(const_int 1 [0x1]) repeated x8
])
(reg:DI 138)
(const_int 2 [0x2]) repeated x2
(const_int 1 [0x1])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem/c:RVVMF4HI (reg:DI 144) [1 v+0 S16 A128])
(unspec:RVVMF4HI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "vsetvl.c":8:1 3450 {*pred_movrvvmf4hi}
(expr_list:REG_DEAD (reg:DI 144)
(nil)))
rescanning insn with uid = 5.
verify found no changes in insn with uid = 5.
Successfully to match this instruction: (insn 5 4 23 2 (set (reg/v:RVVMF4HI 137
[ v ])
(if_then_else:RVVMF4HI (unspec:RVVMF64BI [
(const_vector:RVVMF64BI [
(const_int 1 [0x1]) repeated x8
])
(const_int 1 [0x1])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(mem/c:RVVMF4HI (reg:DI 144) [1 v+0 S16 A128])
(unspec:RVVMF4HI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))) "vsetvl.c":8:1 3450 {*pred_movrvvmf4hi}
(expr_list:REG_DEAD (reg:DI 144)
(nil)))
